• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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    • 专利摘要:
    PURPOSE: A circuit for generating a temperature compensated self refresh basic period is provided to minimize current consumption by adjusting dividing and controlling a basic period itself constantly. CONSTITUTION: A current supply part(62) supplies a current. A control part(64) controls the current supplied from the current supply part variably by a temperature compensation signal according to temperature variation during an extended mode register set operation. And an oscillation part(66) outputs a temperature compensated self refresh basic period signal having a constant period by compensating the temperature variation according to the current being output from the control part.
    公开号:KR20040019151A
    申请号:KR1020020050404
    申请日:2002-08-26
    公开日:2004-03-05
    发明作者:윤혁수
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Temperature compensated self refresh basic cycle generator circuit {Temperature compensated self refresh circuit}
    [6] The present invention relates to a temperature compensated self refresh basic cycle generating circuit, and more particularly, to a temperature compensated self refresh signal TSCR70, TSCR45, TSCR15, TSCR85 set during an extended mode register set (EMRS) operation. The present invention relates to a temperature compensating self refresh basic cycle generating circuit which minimizes current consumption by outputting a constant self refresh basic cycle even with temperature changes.
    [7] In general, self-refresh is a semiconductor memory device, such as a DRAM (dynamic random access memory), which refreshes itself with a certain period or basic period internally to maintain data stored in a memory cell in a standby state. Means to do.
    [8] However, when the temperature increases during the self-refresh operation, the basic period for determining the self-refresh cycle should be faster, but normal operation is performed, but the temperature characteristic of the basic cycle generator for generating the basic period for determining the self-refresh cycle operates in reverse. The higher the value is, the slower the result is, and the normal operation is not performed.
    [9] In other words, when the temperature increases, the basic cycle is slowed down, and the self-refresh cycle is also slowed down by being controlled by the slowed basic cycle, thereby preventing normal operation.
    [10] To this end, in order to compensate for the basic period in accordance with the change in temperature, in the prior art, the self-refresh dispensing is set in advance so that when the temperature change occurs, the basic period is determined according to the division. However, since the basic period is determined only by the dispensing already set, there is a problem in that it cannot cope with various temperature changes.
    [11] In addition, the conventional basic cycle generating circuit has a problem that the basic cycle itself is changed in the process of compensating for the change in the cycle according to the change in temperature, there is a problem that the current loss increases at room temperature and low temperature.
    [12] An object of the present invention for solving the above problems, by adjusting the frequency division to more finely compensate for the change in the cycle according to the change in temperature during the EMRS operation, by controlling the current cycle to maintain a constant constant current consumption To provide a temperature compensation self-refresh basic cycle generator circuit that minimizes the
    [1] 1 is a block diagram of an initialization device of a temperature compensated self refresh circuit according to the present invention;
    [2] 2 is a detailed circuit diagram of a mode register 40 according to the present invention.
    [3] 3 is a detailed circuit diagram of a TSCR decoder 50 according to the present invention.
    [4] 4 is a detailed circuit diagram of a basic period generator 60 according to the present invention.
    [5] 5 is an operation timing diagram of FIG. 4.
    [13] According to an aspect of the present invention, there is provided a current supply unit for supplying a current, a controller for variably controlling and outputting a current supplied from the current supply unit according to a temperature change during an extended mode register set operation; Comprising an oscillation unit for outputting a temperature compensation self-refresh basic cycle signal having a predetermined period by compensating for the temperature change in accordance with the current output from the control unit.
    [14] The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
    [15] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [16] 1 is a configuration diagram of an initialization device of a temperature compensated self refresh circuit according to the present invention.
    [17] The initialization device of the Temperature Compensated Self Refresh (TCSR) circuit is referred to as a clock enable signal CKE (clock enable), a chip select signal CSB (/ chip select), and a lath according to an external command. And a command buffer 10 for outputting a bar signal RASB (/ Row address strobe), a cascade signal CASB (/ column address strobe), and a write enable signal WEB (/ write enable).
    [18] The address buffer 20 outputs bank selection signals BA0, 1 and addresses A1, 2 according to the input address. The EMRS decoder 30 receives the command signals CKE, CSB, RASB, CASB, WEB, and the bank selection signal BA0, 1 applied from the address buffer 20, and receives the mode register set signal EMRS from the command buffer 10. Outputs
    [19] The mode register 40 receives the mode register set signal EMRS applied from the EMRS decoder 30, the addresses A1 and 2 applied from the address buffer 20, and the mode register reset signal RSTM applied from the outside, and receives the self refresh signal TCSR1. Output 2
    [20] The TCSR decoder 50 receives the self refresh signals TCSR1 and 2 applied from the mode register 40 and decodes the self refresh signals TCSR1 and 2 to output the temperature compensated self refresh signals TCSR85, TCSR70, TCSR45, and TCSR15.
    [21] The basic period generator 60 receives the temperature compensation self refresh signals TCSR85, TCSR70, TCSR45, and TCSR15 output from the TCSR decoder 50 to generate an oscillation cycle signal OSCSE for performing a self refresh operation in the self refresh mode.
    [22] 2 is a detailed circuit diagram of a mode register according to the present invention.
    [23] The mode register 40 includes an inverter IV1 inverting and outputting the mode register set signal EMRS applied from the EMRS decoder 30, an inverter IV2 inverting and outputting an output signal of IV1, and an address applied from the address buffer 20. Inverter IV3 for inverting and outputting A1 and 2, and inverter IV4 for inverting and outputting the mode register reset signal RSTM.
    [24] The NAND gate ND1 performs a NAND operation on the output signals applied from the inverters IV3 and IV4 and outputs them. The inverter IV5 inverts the output signal of the NAND gate ND1 and outputs it to the output terminal of the inverter IV3 and the input terminal of the NAND gate ND1. Inverters IV6 and 7 delay the output of NAND gate ND1 to output self-refresh signals TCSR1 and 2.
    [25] 3 is a detailed circuit diagram of a TSCR decoder according to the present invention.
    [26] The TCSR decoder 50 includes an inverter IV8 that inverts and outputs the temperature compensation self refresh signal TCSR1 applied from the mode register 40, and an inverter IV9 that inverts and outputs the temperature compensation self refresh signal TCSR2.
    [27] The NAND gate ND2 NAND-operates the signals applied from the inverters IV8 and IV9, and the NAND gate ND3 NAND-operates the signals applied from the temperature compensation self-refresh signal TCSR1 and the inverter IV9.
    [28] The NAND gate ND4 performs NAND operation on the output signal of the inverter IV8 and the temperature compensation self refresh signal TCSR2, and the NAND gate ND5 performs NAND operation on the temperature compensation self refresh signals TCSR1 and TCSR2. The inverters IV10 to IV13 invert the output signals of the NAND gates ND2 to ND5, respectively, and output the temperature compensation self refresh signals TCSR70, TCSR45, TCSR15, and TCSR85, respectively.
    [29] Here, TCSR70, TCSR45, TCSR15, and TCSR85 are compensation signals according to the case where the temperature is 70 degrees, the 45 degrees, the 15 degrees, and the 85 degrees, respectively.
    [30] 4 is a circuit diagram of a basic period generator according to the present invention.
    [31] The basic period generator 60 includes a current supply unit 62, a controller 64, and an oscillator 66, and outputs the temperature compensation self refresh signals TSCR15, TSCR45, TSCR70, and TSCR85 output from the TSCR decoder 50. Receive and generate a self-refresh basic periodic signal OSCSE.
    [32] The current supply unit 62 includes the PMOS transistors P1 and P2 and is controlled by the fuses M1 and M2 to flow current to the node Node1.
    [33] The control unit 64 includes a load element R1 including PMOS transistors P3 and P7, a load element R2 including PMOS transistors P4 and P8, and a PMOS transistor P5 and P9. A load element R4 including a load element R3 and PMOS transistors P6 and P10 is provided.
    [34] At this time, the PMOS transistors P3 to P6 are connected in parallel with the nodes Node1 in common, and the PMOS transistors P3 to P6 and the PMOS transistors P7 to P10 are connected in series to each other in common with the node Node2. Connected.
    [35] On the other hand, the PMOS transistors P3 to P6 are controlled by the self refresh signals TCSR70, TCSR45, TCSR15, and TCSR85 output from the TCSR decoder 40, respectively, and the PMOS transistors P7 to P10 are the PMOS transistors P3 to P6. Controlled by the output of P6).
    [36] That is, in the case of 70 degree compensation, the node Node2 is set by the load element R1 controlled by TCSR70, and in case of 45 degree compensation, it is set by the load element R2 controlled by TCSR45. In the case of degree compensation, it is set by the load element R3 controlled by TCSR15, and in case of 85 degree compensation, it is set by the load element R4 controlled by TCSR85.
    [37] Therefore, the control unit 64 includes load elements R1 to R4 having different sizes, and functions as a variable resistor by controlling the voltage or current of the node Node2.
    [38] The oscillator 66 includes NMOS transistors N1 to N5 that are controlled and driven by the node Node2 voltage, PMOS transistors P11 to P14 that are controlled and driven by the node Node3 voltage, and PMOS transistors serving as inversions. P15 to P17, the NMOS transistors N6 to N8, and the transistors P18, P19, N9, and N10 serving as capacitors output the self-refresh basic period signal OSCSE.
    [39] Here, when the output self-refreshing basic period signal OSCSE is high level, the NMOS transistor N6 is driven to apply a low level signal to the PMOS transistors P16 and P18 to drive the high level signal to the NMOS transistor N8. It is applied to drive and outputs the low level self refresh basic period signal OSCSE.
    [40] In this way, the voltage of the node Node2 is controlled by the temperature compensation self refresh signals TCSR70, TCSR45, TCSR15, and TCSR85 output from the TCSR decoder 50 according to the temperature level, and the voltage of the node Node3 is controlled by the voltage of the node Node2. Controlled.
    [41] FIG. 5 is an operation timing diagram of FIG. 4, and illustrates a timing diagram of a basic periodic signal OSCSE compensated for a change in temperature by temperature compensation self refresh signals TCSR70, TCSR45, TCSR15, and TCSR85 according to temperature.
    [42] 5A is an operation timing diagram when the temperature is 25 degrees in the normal mode, and (b) is an operation timing diagram when the temperature rises to 70 degrees in the normal mode, and the temperature is 25 degrees. It can be seen that the cycle becomes slow when the temperature rises to 70 degrees rather than the basic cycle.
    [43] As shown in (b), the basic periods compensated by the respective temperature compensation signals in the case where the basic period is changed by the temperature change are shown in (c) to (f).
    [44] First, (c) is a timing diagram when the temperature is 70 degrees and is compensated by the signal TCSR85 for compensating 85 degrees, and is further compensated by 15 degrees, which is a difference between 85 degrees and 70 degrees, so that the period of the timing diagram is (a). The timing of is also faster than the period.
    [45] (d) is a timing diagram when the temperature is 70 degrees and is compensated by the signal TCSR70 for compensating 70 degrees, and it can be seen that it is compensated in the same manner as the normal basic period of (a).
    [46] (e) is a timing diagram when the temperature is 70 degrees and is compensated by the signal TCSR45 for compensating 45 degrees, and is compensated less by 25 degrees, which is a difference between 45 degrees and 70 degrees, so that the period of the timing diagram is the timing of (a). It can be seen that it is slower than the degree period.
    [47] (f) is a timing diagram when the temperature is 70 degrees and is compensated by the signal TCSR15 for compensating 15 degrees, and is compensated less by 55 degrees, which is a difference between 15 and 70 degrees, so that the period of the timing diagram is the timing of (a). It may be slower than the period of degrees, and much slower than the period of the timing diagram shown in (e).
    [48] In this manner, the self-refresh cycle can be accurately adjusted during the self-refresh operation by keeping the basic period constant by using the temperature compensation self-refresh signals TSCR15, TSCR45, TSCR70, and TSCR85 output according to the temperature.
    [49] As described above, the temperature compensation self-refresh basic cycle generating circuit according to the present invention can finely and accurately adjust the cycle of self-refresh to reduce defects caused by the refresh failure due to temperature change, and maintain the basic cycle itself. By doing so, there is an effect that can minimize the current consumption according to the temperature change.
    [50] In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] A current supply unit supplying current;
    A controller for variably controlling and outputting a current supplied from the current supply unit according to a temperature change in an extended mode register set operation by a temperature compensation signal; And
    Compensating the temperature change in accordance with the current output from the control unit temperature compensation self-refresh basic cycle generating circuit including an oscillation unit for outputting a temperature compensation self-refresh basic cycle signal having a certain period.
    [2" claim-type="Currently amended] The method of claim 1, wherein the control unit,
    A first resistor unit controlled by a temperature compensation signal according to the temperature change;
    A second resistor unit connected in parallel with the first resistor unit and controlled by the temperature compensation signal;
    A third resistor connected in parallel with the second resistor and controlled by the temperature compensation signal; And
    And a fourth resistor unit connected in parallel with the third resistor unit and controlled by the temperature compensation signal.
    [3" claim-type="Currently amended] The method of claim 1, wherein the oscillator,
    Temperature compensation self-refreshing basic cycle generating circuit, characterized in that to maintain the basic cycle in accordance with the temperature change constant.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-08-26|Application filed by 주식회사 하이닉스반도체
    2002-08-26|Priority to KR1020020050404A
    2004-03-05|Publication of KR20040019151A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020050404A|KR20040019151A|2002-08-26|2002-08-26|Temperature compensated self refresh circuit|
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